module MACArraySetUp(
  input         clock,
  input         reset,
  input  [71:0] io_dataIn,
  input  [7:0]  io_wAddr,
  input         io_valid,
  input         io_clear,
  input         io_lastvec,
  input         io_switch,
  output [23:0] io_nextRow,
  output        io_switchOut_0,
  output        io_switchOut_1,
  output        io_switchOut_2,
  output [7:0]  io_waddrOut,
  output        io_weOut,
  output        io_clearOut,
  output        io_doneOut
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
`endif // RANDOMIZE_REG_INIT
  reg [7:0] firstColumnReg_0; // @[macarraySetup.scala 33:37]
  reg [7:0] firstColumnReg_1; // @[macarraySetup.scala 33:37]
  reg [7:0] firstColumnReg_2; // @[macarraySetup.scala 33:37]
  reg  switchReg_0; // @[macarraySetup.scala 52:32]
  reg  switchReg_1; // @[macarraySetup.scala 52:32]
  reg  switchReg_2; // @[macarraySetup.scala 52:32]
  reg [7:0] io_waddrOut_r; // @[Reg.scala 16:16]
  reg [7:0] io_waddrOut_r_1; // @[Reg.scala 16:16]
  reg [7:0] io_waddrOut_r_2; // @[Reg.scala 16:16]
  reg [7:0] io_waddrOut_r_3; // @[Reg.scala 16:16]
  reg  io_weOut_r; // @[Reg.scala 16:16]
  reg  io_weOut_r_1; // @[Reg.scala 16:16]
  reg  io_weOut_r_2; // @[Reg.scala 16:16]
  reg  io_weOut_r_3; // @[Reg.scala 16:16]
  reg  io_clearOut_r; // @[Reg.scala 16:16]
  reg  io_clearOut_r_1; // @[Reg.scala 16:16]
  reg  io_clearOut_r_2; // @[Reg.scala 16:16]
  reg  io_clearOut_r_3; // @[Reg.scala 16:16]
  reg  io_doneOut_r; // @[Reg.scala 16:16]
  reg  io_doneOut_r_1; // @[Reg.scala 16:16]
  reg  io_doneOut_r_2; // @[Reg.scala 16:16]
  reg [7:0] diagnonalWire_1_r; // @[Reg.scala 16:16]
  reg [7:0] diagnonalWire_0_r; // @[Reg.scala 16:16]
  reg [7:0] diagnonalWire_0_r_1; // @[Reg.scala 16:16]
  wire [15:0] io_nextRow_hi = {firstColumnReg_0,diagnonalWire_1_r}; // @[macarraySetup.scala 75:37]
  assign io_nextRow = {io_nextRow_hi,diagnonalWire_0_r_1}; // @[macarraySetup.scala 75:37]
  assign io_switchOut_0 = switchReg_0; // @[macarraySetup.scala 67:22]
  assign io_switchOut_1 = switchReg_1; // @[macarraySetup.scala 67:22]
  assign io_switchOut_2 = switchReg_2; // @[macarraySetup.scala 67:22]
  assign io_waddrOut = io_waddrOut_r_3; // @[macarraySetup.scala 62:21]
  assign io_weOut = io_weOut_r_3; // @[macarraySetup.scala 63:18]
  assign io_clearOut = io_clearOut_r_3; // @[macarraySetup.scala 64:21]
  assign io_doneOut = io_doneOut_r_2; // @[macarraySetup.scala 65:20]
  always @(posedge clock) begin
    if (reset) begin // @[macarraySetup.scala 33:37]
      firstColumnReg_0 <= 8'h0; // @[macarraySetup.scala 33:37]
    end else begin
      firstColumnReg_0 <= io_dataIn[7:0]; // @[macarraySetup.scala 39:35]
    end
    if (reset) begin // @[macarraySetup.scala 33:37]
      firstColumnReg_1 <= 8'h0; // @[macarraySetup.scala 33:37]
    end else begin
      firstColumnReg_1 <= io_dataIn[15:8]; // @[macarraySetup.scala 39:35]
    end
    if (reset) begin // @[macarraySetup.scala 33:37]
      firstColumnReg_2 <= 8'h0; // @[macarraySetup.scala 33:37]
    end else begin
      firstColumnReg_2 <= io_dataIn[23:16]; // @[macarraySetup.scala 39:35]
    end
    if (reset) begin // @[macarraySetup.scala 52:32]
      switchReg_0 <= 1'h0; // @[macarraySetup.scala 52:32]
    end else begin
      switchReg_0 <= io_switch; // @[macarraySetup.scala 55:38]
    end
    if (reset) begin // @[macarraySetup.scala 52:32]
      switchReg_1 <= 1'h0; // @[macarraySetup.scala 52:32]
    end else begin
      switchReg_1 <= switchReg_0; // @[macarraySetup.scala 57:38]
    end
    if (reset) begin // @[macarraySetup.scala 52:32]
      switchReg_2 <= 1'h0; // @[macarraySetup.scala 52:32]
    end else begin
      switchReg_2 <= switchReg_1; // @[macarraySetup.scala 57:38]
    end
    io_waddrOut_r <= io_wAddr; // @[Reg.scala 16:16 17:{18,22}]
    io_waddrOut_r_1 <= io_waddrOut_r; // @[Reg.scala 16:16 17:{18,22}]
    io_waddrOut_r_2 <= io_waddrOut_r_1; // @[Reg.scala 16:16 17:{18,22}]
    io_waddrOut_r_3 <= io_waddrOut_r_2; // @[Reg.scala 16:16 17:{18,22}]
    io_weOut_r <= io_valid; // @[Reg.scala 16:16 17:{18,22}]
    io_weOut_r_1 <= io_weOut_r; // @[Reg.scala 16:16 17:{18,22}]
    io_weOut_r_2 <= io_weOut_r_1; // @[Reg.scala 16:16 17:{18,22}]
    io_weOut_r_3 <= io_weOut_r_2; // @[Reg.scala 16:16 17:{18,22}]
    io_clearOut_r <= io_clear; // @[Reg.scala 16:16 17:{18,22}]
    io_clearOut_r_1 <= io_clearOut_r; // @[Reg.scala 16:16 17:{18,22}]
    io_clearOut_r_2 <= io_clearOut_r_1; // @[Reg.scala 16:16 17:{18,22}]
    io_clearOut_r_3 <= io_clearOut_r_2; // @[Reg.scala 16:16 17:{18,22}]
    io_doneOut_r <= io_lastvec; // @[Reg.scala 16:16 17:{18,22}]
    io_doneOut_r_1 <= io_doneOut_r; // @[Reg.scala 16:16 17:{18,22}]
    io_doneOut_r_2 <= io_doneOut_r_1; // @[Reg.scala 16:16 17:{18,22}]
    diagnonalWire_1_r <= firstColumnReg_1; // @[Reg.scala 16:16 17:{18,22}]
    diagnonalWire_0_r <= firstColumnReg_2; // @[Reg.scala 16:16 17:{18,22}]
    diagnonalWire_0_r_1 <= diagnonalWire_0_r; // @[Reg.scala 16:16 17:{18,22}]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  firstColumnReg_0 = _RAND_0[7:0];
  _RAND_1 = {1{`RANDOM}};
  firstColumnReg_1 = _RAND_1[7:0];
  _RAND_2 = {1{`RANDOM}};
  firstColumnReg_2 = _RAND_2[7:0];
  _RAND_3 = {1{`RANDOM}};
  switchReg_0 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  switchReg_1 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  switchReg_2 = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  io_waddrOut_r = _RAND_6[7:0];
  _RAND_7 = {1{`RANDOM}};
  io_waddrOut_r_1 = _RAND_7[7:0];
  _RAND_8 = {1{`RANDOM}};
  io_waddrOut_r_2 = _RAND_8[7:0];
  _RAND_9 = {1{`RANDOM}};
  io_waddrOut_r_3 = _RAND_9[7:0];
  _RAND_10 = {1{`RANDOM}};
  io_weOut_r = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  io_weOut_r_1 = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  io_weOut_r_2 = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  io_weOut_r_3 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  io_clearOut_r = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  io_clearOut_r_1 = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  io_clearOut_r_2 = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  io_clearOut_r_3 = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  io_doneOut_r = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  io_doneOut_r_1 = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  io_doneOut_r_2 = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  diagnonalWire_1_r = _RAND_21[7:0];
  _RAND_22 = {1{`RANDOM}};
  diagnonalWire_0_r = _RAND_22[7:0];
  _RAND_23 = {1{`RANDOM}};
  diagnonalWire_0_r_1 = _RAND_23[7:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
